1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit including a test circuit.
2. Description of Related Art
With the recent remarkable development of technology for semiconductor integrated circuits, multiple circuit blocks that operate based on clocks of different frequencies may be incorporated into a single circuit chip. In such a case, both a logic test and a delay test are usually carried out to secure the reliability of the circuit chip.
Japanese Unexamined Patent Application Publication No. 56-168268 discloses a technique for diagnosing asynchronous operation by use of a scan-in/scan-out technique. Japanese Unexamined Patent Application Publication No. 56-168268 discloses the technique in which all flip-flop circuits in logic circuits to be diagnosed are configured as a series of shift registers during a test, and setting of a state (scan-in) and reading of a state (scan-out) are carried out by shift operation, thereby testing the logic circuits to be diagnosed as a combinational circuit.